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M68AW256DL
4 Mbit (256K x16) 3.0V Asynchronous SRAM
FEATURES SUMMARY s SUPPLY VOLTAGE: 2.7 to 3.6V
s s s s s s s s
Figure 1. Packages
256K x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55ns SINGLE BYTE READ/WRITE LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN DUAL CHIP ENABLE for EASY DEPTH EXPANSION
BGA
1 44
TSOP44 Type II (ND)
TFBGA48 (ZB) 7 x 8 mm
June 2002
1/20
M68AW256DL
TABLE OF CONTENTS SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. Address Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . 10 Figure 10. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . 10 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 11. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 12. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 13. UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 14. E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 15. E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . 15 Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TSOP44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . . . . . . . . . . 16 TSOP 44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data . . . . . . . 16 TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . . . . . . . . . 17 TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . . . . . . . . . 17 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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M68AW256DL
SUMMARY DESCRIPTION The M68AW256DL is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 262,144 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an au-
tomatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW256DL is available in TFBGA48 (0.75 mm pitch) and in TSOP44 Type II packages.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A17 Address Inputs Data Input/Output Chip Enables Output Enable Write Enable Upper Byte Enable Input Lower Byte Enable Input Supply Voltage Ground Not Connected Internally Don't Use as Internally Connected
VCC
DQ0-DQ15 E1, E2
18 A0-A17 W
16 DQ0-DQ15
G W UB
E1 E2 G UB LB
M68AW256DL
LB VCC VSS NC DU
VSS
AI05492
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M68AW256DL
Figure 3. TSOP Connections
A4 A3 A2 A1 A0 E1 DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 W A16 A15 A14 A13 A12
1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 M68AW256DL 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23
AI05493
A5 A6 A7 G UB LB DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 E2 A8 A9 A10 A11 A17
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M68AW256DL
Figure 4. TFBGA Connections (Top view through package)
1 2 3 4 5 6
A
LB
G
A0
A1
A2
E2
B
DQ8
UB
A3
A4
E1
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
A17
A7
DQ3
VCC
E
VCC
DQ12
NC
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
NC
A12
A13
W
DQ7
H
NC
A8
A9
A10
A11
DU
AI05494
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M68AW256DL
Figure 5. Block Diagram
A17 ROW DECODER A7 MEMORY ARRAY
DQ15 UB
(8)
I/O CIRCUITS COLUMN DECODER
DQ0 E1 E2 UB LB Ex LB
(8)
A0 (8)
A6
W
UB
(8) LB G
AI05495
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 2. Absolute Maximum Ratings
Symbol IO (1) TA TSTG V CC VIO (2) PD Output Current Ambient Operating Temperature Storage Temperature Supply Voltage Input or Output Voltage Power Dissipation Parameter
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Value 20 -55 to 125 -65 to 150 -0.5 to 4.6 -0.5 to VCC +0.5 1
Unit mA C C V V W
Note: 1. One output at a time, not to exceed 1 second duration. 2. Up to a maximum operating VCC of 3.6V only.
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M68AW256DL
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter VCC Supply Voltage Range 1 Ambient Operating Temperature Range 6 Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R 2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Output Transition Timing Ref. Voltages -40 to 85C 30pF 3.0k 3.1k 1ns/V 0 to VCC VCC/2 VRL = 0.3VCC; VRH = 0.7VCC M68AW256ML 2.7 to 3.6V 0 to 70C
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
VCC
I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST CL I/O Transition Timing Reference Voltage VCC 0.7VCC 0.3VCC
AI04831
OUT
R2
0V
CL includes probe and 1 TTLcapacitance
AI05832
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M68AW256DL
Table 4. Capacitance
Symbol C IN C OUT(3) Parameter (1,2) Input Capacitance on all pins (except DQ) Output Capacitance Test Conditio n VIN = 0V VOUT = 0V Min Max 8 10 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. At TA = 25C, f = 1 MHz, VCC = 3.0V. 3. Outputs deselected.
Table 5. DC Characteristics
Symbol ICC1 (1,2) ICC2 (3) Parameter Operating Supply Current Test Condition VCC = 3.6V, f = 1/tAVAV, IOUT = 0mA VCC = 3.6V, f = 1MHz, I OUT = 0mA V CC = 3.6V, f = 0, E1 VCC -0.2V or E2 0.2V or LB=UB VCC -0.2V 0V VIN V CC 0V VOUT VCC -1 -1 2.2 -0.3 IOH = -1.0mA IOL = 2.1mA 2.4 0.4 5 70ns 55ns Min Typ Max 20 26 2 Unit mA mA mA
Operating Supply Current
ISB ILI ILO (4) VIH V IL VOH VOL
Note: 1. 2. 3. 4.
Standby Supply Current CMOS Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage
10 1 1 VCC + 0.3 0.6
A A A V V V V
Average AC current, cycling at tAVAV minimum. E1 = VIL, E2 = VIH, LB or/and UB = VIL, VIN = VIL or VIH. E1 0.2V or E2 VCC -0.2V, LB or/and UB 0.2V, VIN 0.2V or VIN VCC -0.2V. Output disabled.
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M68AW256DL
OPERATION The M68AW256DL has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E1 = High) or Chip Select is asserted (E2 = Low), or UB/ LB are de-asserted (UB/LB = High). An Output Enable (G) signal provides a high speed tri-state conTable 6. Operating Modes
Operation Deselected Deselected Deselected Lower Byte Read Lower Byte Write Output Disabled Upper Byte Read Upper Byte Write Word Read Word Write
Note: X = VIH or VIL.
trol, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E1, LB and UB as summarized in the Operating Modes table (see Table 6).
E1 VIH X X V IL V IL V IL V IL V IL V IL V IL
E2 X VIL X VIH VIH VIH VIH VIH VIH VIH
W X X X VIH VIL VIH VIH VIL VIH VIL
G X X X VIL X VIH VIL X VIL X
LB X X VIH VIL VIL X VIH VIH VIL VIL
UB X X VIH VIH VIH X VIL VIL VIL VIL
DQ0-DQ7 Hi-Z Hi-Z Hi-Z Data Output Data Input Hi-Z Hi-Z Hi-Z Data Output Data Input
DQ8-DQ15 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Data Output Data Input Data Output Data Input
Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Read Mode The M68AW256DL, when Chip Select (E2) is High, is in the read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E1) is asserted. This provides access to data from eight or sixteen, depending on the status of the signal UB and LB, of the 4,194,304 locations in the static memory array, specified by the 18 address inputs. Valid data will be available at the
eight or sixteen output pins within tAVQV after the last stable address, providing G is Low and E1 is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV, tGLQV or tBLQV) rather than the address. Data out may be indeterminate at tELQX, tGLQX and tBLQX, but data lines will always be valid at tAVQV.
Figure 8. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A17 tAVQV VALID tAXQX
DQ0-DQ7 and/or DQ8-DQ15
DATA VALID
AI03956
Note: E1 = Low, E2 = High, G = Low, W = High, UB = Low and/or LB = Low.
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M68AW256DL
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV A0-A17 tAVQV tELQV E1 VALID tAXQX tEHQZ
E2
tELQX tGLQV G tGLQX DQ0-DQ15 tBLQV UB, LB tBLQX
AI05496
tGHQZ
VALID tBHQZ
Note: Writ e Enable (W) = High.
Figure 10. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms
E1, UB, LB
E2 ICC ISB tPU 50%
AI05497
tPD
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M68AW256DL
Table 7. Read and Standby Mode AC Characteristics
M68AW256DL Symbol tAVAV tAVQV tAXQX (1) tBHQZ (2,3) tBLQV tBLQX (1) tEHQZ (2,3) tELQV tELQX (1) tGHQZ (2,3) tGLQV tGLQX (2) tPD (4) tPU (4) Read Cycle Time Address Valid to Output Valid Data hold from address change Upper/Lower Byte Enable High to Output Hi-Z Upper/Lower Byte Enable Low to Output Valid Upper/Lower Byte Enable Low to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable or UB/LB High to Power Down Chip Enable or UB/LB Low to Power Up Parameter 55 Min Max Min Max Max Min Max Max Min Max Max Min Max Min 55 55 5 20 55 5 20 55 5 20 25 5 0 55 70 70 70 5 25 70 5 25 70 5 25 35 5 0 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX, tBHQZ is less than tBLQX and tEHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Tested initially and after any design or process changes that may affect these parameters.
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M68AW256DL
Write Mode The M68AW256DL, when Chip Select (E2) is High, is in the Write Mode whenever the W and E1 are Low. Either the Chip Enable Input (E1) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. When E1 or W is Low, and UB or LB is Low, write cycle begins on the W or E1 falling edge. When E1 and W are Low, and UB = LB = High, write cycle begins on the first falling edge of UB or LB. Therefore, address setup time is referenced to Write Enable, Chip Enables and UB/LB as tAVWL, tAVEL and tAVBL respectively, and is determined by the latter occurring falling edge.
The Write cycle can be terminated by the earlier rising edge of E1, W, UB and LB. If the Output is enabled (E1 = Low, E2 = High, G = Low, LB or UB = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E1 or for tDVBH before the rising edge of UB/LB, whichever occurs first, and remain valid for tWHDX, tEHDX and tBHDX respectively.
Figure 11. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A17 VALID tAVWH tAVEL E1 tELWH tWHAX
E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ15 DATA INPUT tDVWH tBLBH UB, LB
AI05498
tWHQX
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M68AW256DL
Figure 12. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A17 VALID tAVEH tAVEL E1 tELEH tEHAX
E2 tAVWL W tEHDX DQ0-DQ15 DATA INPUT tDVEH tBLBH UB, LB
AI05425
tWLEH
Figure 13. UB/LB Controlled, Write AC Waveforms
tAVAV A0-A17 VALID tAVBH E1 tBHAX
E2 tAVWL W tWLQZ DQ0-DQ15 DATA (1) tBHDX DATA INPUT tDVBH tAVBL UB, LB
AI05426
tWLBH
tBLBH
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
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M68AW256DL
Table 8. Write Mode AC Characteristics
M68AW256DL Symbol tAVAV tAVBH tAVBL tAVEH tAVEL tAVWH t AVWL tBHAX tBHDX tBLBH tBLEH tBLWH tDVBH tDVEH tDVWH tEHAX tEHDX tELBH tELEH tELWH tWHAX tWHDX tWHQX (1) tWLBH tWLEH tWLQZ (1,2) tWLWH Write Cycle Time Address Valid to LB, UB High Addess Valid to LB, UB Low Address Valid to Chip Enable High Address valid to Chip Enable Low Address Valid to Write Enable High Address Valid to Write Enable Low LB, UB High to Address Transition LB, UB High to Input Transition LB, UB Low to LB, UB High LB, UB Low to Chip Enable High LB, UB Low to Write Enable High Input Valid to LB, UB High Input Valid to Chip Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip enable High to Input Transition Chip Enable Low to LB, UB High Chip Enable Low to Chip Enable High Chip Enable Low to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to LB, UB High Write Enable Low to Chip Enable High Write Enable Low to Output Hi-Z Write Enable Low to Write Enable High Parameter 55 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min 55 45 0 45 0 45 0 0 0 45 45 45 25 25 25 0 0 45 45 45 0 0 5 45 45 20 45 70 70 60 0 60 0 60 0 0 0 60 60 60 30 30 30 0 0 60 60 60 0 0 5 60 60 20 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
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M68AW256DL
Figure 14. E1 Controlled, Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 3.6V VCC 2.7V
VDR > 1.5V tCDR E1 VDR -0.2V or UB=LB > VDR -0.2V E1, UB/LB tR
AI05456
Figure 15. E2 Controlled, Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 3.6V VCC 2.7V
VDR > 1.5V tCDR E2 E2 0.2V
AI05457
tR
Table 9. Low VCC Data Retention Characteristics
Symbol Parameter Test Condition VCC = 1.5V, E1 VCC -0.2V or E2 0.2V or UB = LB V CC -0.2V, f =0 t CDR (1,2) tR (2) VDR (1) Chip Deselected to Data Retention Time Operation Recovery Time Supply Voltage (Data Retention) E1 VCC -0.2V or E2 0.2V or UB = LB V CC -0.2V, f = 0 0 tAVAV 1.5 ns ns V Min Typ 4.5 Max 9 Unit A
ICCDR (1) Supply Current (Data Retention)
Note: 1. All other Inputs at VIH VCC -0.2V or VIL 0.2V. 2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V.
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M68AW256DL
PACKAGE MECHANICAL Figure 16. TSOP44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Outline
D
N
E1
E
1
N/2
ZD
b
e
A
A2 C CP A1 L
TSOP-d
Note: Drawing is not to scale.
Table 10. TSOP 44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data
Symbol A A1 A2 b c D E E1 e L ZD alfa CP N 44 18.410 11.760 10.160 0.800 0.500 0.805 0.350 0.120 - - - - 0.400 - 0 0.210 - - - - 0.600 - 5 0.100 44 0.7248 0.4630 0.4000 0.0315 0.0197 0.0317 0.050 0.950 millimeters Typ Min Max 1.200 0.150 1.050 0.0138 0.0047 - - - - 0.0157 - 0 0.0083 - - - - 0.0236 - 5 0.0039 0.0020 0.0374 Typ inches Min Max 0.0472 0.0059 0.0413
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M68AW256DL
Figure 17. TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline
D FD FE SD D1
SE E E1 BALL "A1" ddd
e e A A1 b A2
BGA-Z22
Note: Drawing is not to scale.
Table 11. TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 8.000 5.250 0.750 1.625 1.375 0.375 0.375 7.900 - - - - - - 0.400 7.000 3.750 0.300 6.900 - Min 1.010 0.260 0.950 0.500 7.100 - 0.100 8.100 - - - - - - 0.3150 0.2067 0.0295 0.0640 0.0541 0.0148 0.0148 0.3110 - - - - - - 0.0157 0.2756 0.1476 0.0118 0.2717 - Max 1.200 Typ Min 0.0398 0.0102 0.0374 0.0197 0.2795 - 0.0039 0.3189 - - - - - - Max 0.0472 inches
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M68AW256DL
PART NUMBERING Table 12. Ordering Information Scheme
Example: Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 256 = 4 Mbit (256K x16) Optio n 1 D = 2 Chip Enable; Write and Standby from UB and LB Optio n 2 L = Low Leakage Speed Class 55 = 55 ns 70 = 70 ns Package ND = TSOP 44 Type II ZB = TFBGA48: 0.75 mm pitch Operative Temperature 1 = 0 to 70 C 6 = -40 to 85 C Shipping T = Tape & Reel Packing M68AW256 D L 55 ZB 6 T
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M68AW256DL
REVISION HISTORY Table 13. Document Revision History
Date February 2002 14-Mar-2002 07-Jun-2002 Version -01 -02 -03 First Issue Tables 3, 5, 7 and 9 clarified Figures 3, 8, 9, 11, 12, 13 and 14 clarified ICCDR clarified (Table 9) ISB clarified (Table 5) Revision Details
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M68AW256DL
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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